1. 山东理工大学 计算机科学与技术学院,山东 淄博 255000
2. 重庆大学 自动化学院,重庆 400044
[ "李钊(1983—),男,副教授,E-mail:[email protected];" ]
[ "黄程程(1997—),男,山东理工大学硕士研究生,E-mail:[email protected];" ]
[ "何益智(1995—),男,山东理工大学硕士研究生,E-mail:[email protected];" ]
[ "苏晓杰(1985—),男,教授,E-mail:[email protected]。" ]
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李钊, 黄程程, 何益智, 等. Winograd转置卷积快速实现方法研究[J]. 西安电子科技大学学报, 2023,50(6):148-160.
李钊, 黄程程, 何益智, 等. Winograd转置卷积快速实现方法研究[J]. 西安电子科技大学学报, 2023,50(6):148-160. DOI: 10.19665/j.issn1001-2400.20230308.
Winograd转置卷积算法是现场可编程门阵列中广泛使用的卷积加速方法,可通过分组后执行Winograd卷积来解决转置卷积的零填充问题。然而该方法需要对输入特征映射和卷积核进行分组运算,且需要对运算结果进行重组,以生成完整的输出特征映射,复杂的元素坐标计算增加了设计的复杂度。针对上述问题,提出一种采用统一转换矩阵计算Winograd转置卷积的方法,使用统一的转换矩阵代替对输入特征映射和卷积核进行分组,有效解决了重叠求和、零填充、卷积核翻转、分解和重组等问题。并在该方法的指导下,结合数据重用、双缓冲区设计和流水线等方法,完成了现场可编程门阵列上转置卷积的加速器的设计。选择高斯-泊松生成对抗网络进行实验验证,并与主流的转置卷积设计方法进行了综合比较。实验结果表明,提出的方法可有效降低资源消耗和功耗,加速器的有效性能比现有的转置卷积方法提高了约1.13至23.92倍。
The Winograd transposed convolution algorithm is a widely used convolution acceleration method for Field Programmable Gate Array(FPGA).It can solve the zero-padding problem of transposed convolution by performing the Winograd convolution after grouping.However,this method requires grouping operation on the input feature map and convolution kernel,and needs to reorganize the operation results to generate a complete output feature map.The complex calculation of element coordinates increases the difficulty of design.To solve the above problems,a Winograd transposed convolution method based on the unified transformation matrix is proposed,which uses the unified transformation matrix instead of grouping the input feature map and convolution kernel,and effectively solves the problems of overlapping summation,zero padding,convolution kernel inversion,decomposition and reorganization.And under the guidance of the Winograd transpose convolution method based on the unified transformation matrix,combined with data reuse,the double buffer and the pipeline,the design of a transposed convolution accelerator on FPGA is completed.The Gaussian-Poisson generative adversarial network is selected for experimental verification,and compared with the mainstream transposed convolution method.Experimental results show that the proposed method can effectively reduce the resource consumption and power consumption,and that the effective performance of the accelerator is 1.13x~23.92x higher than that of the existing transposed convolution methods.
统一转换矩阵Winograd转置卷积现场可编程门阵列加速器
unified transformation matrixWinograd transposed convolutionfield programmable gate arrayaccelerator
YU J, HU Y, NING X, et al. Instruction Driven Cross-Layer CNN Accelerator with Winograd Transformation on FPGA[C]// 2017 International Conference on Field Programmable Technology(ICFPT).Piscataway:IEEE, 2017:227-230.
LU L, LIANG Y, XIAO Q, et al. Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs[C]// 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines(FCCM).Piscataway:IEEE, 2017:101-108.
SHEN J, HUANG Y, WANG Z, et al. Towards a Uniform Template-Based Architecture for Accelerating 2D and 3D CNNs on FPGA[C]// The 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays(FPGA'18). New York: ACM, 2018:97-106.
LIU X Y, POOL J, HAN S, et al. Efficient Sparse-Winograd Convolutional Neural Network[C]// Proceedings of the 6th International Conference on Learning Representations(ICLR 2018).Appleton:ICLR, 2018:1-10.
WEI X, YU C, ZHANG P, et al. Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs[C]// 2017 54th ACM/EDAC/IEEE Design Automation Conference(DAC).Piscataway:IEEE, 2017:1-6.
YANG C, WANG Y, WANG X, et al. WRA:A 2.2-to-6.3 TOPS Highly Unified Dynamically Reconfigurable Accelerator Using a Novel Winograd Decomposition Algorithm for Convolutional Neural Networks[J]. IEEE Transactions on Circuits and Systems I:Regular Papers, 2019, 66(9):3480-3493. DOI:10.1109/TCSI.8919http://doi.org/10.1109/TCSI.8919https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919
YEPEZ J, KO S B. Stride 2 1-D,2-D,and 3-D Winograd for Convolutional Neural Networks[J]. IEEE Transactions on Very Large Scale Integration Systems, 2020, 28(4):853-863. DOI:10.1109/TVLSI.92http://doi.org/10.1109/TVLSI.92https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=92https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=92
DENG H, WANG J, YE H, et al. 3D-VNPU:A Flexible Accelerator for 2D/3D CNNs on FPGA[C]// Proceedings of the IEEE International Symposium on Field-Programmable Custom Computing Machines(FCCM 2021).Piscataway:IEEE, 2021:181-185.
SHEN J, HUANG Y, WEN M, et al. Toward an Efficient Deep Pipelined Template-Based Architecture for Accelerating the Entire 2-D and 3-D CNNs on FPGA[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, 39(7):1442-1455. DOI:10.1109/TCAD.43http://doi.org/10.1109/TCAD.43https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=43
WANG Z L, LAN Q, HE H J, et al. Winograd Algorithm for 3D Convolution Neural Networks[C]// Proceedings of the 26th International Conference on Artificial Neural Networks(ICANN 2017).Berlin:Springer, 2017:609-616.
KIM M, PARK C, KIM S, et al. Efficient Dilated-Winograd Convolutional Neural Networks[C]// 2019 IEEE International Conference on Image Processing(ICIP).Piscataway:IEEE, 2019:2711-2715.
DING W, HUANG Z Y, HUANG Z K, et al. Designing Efficient Accelerator of Depthwise Separable Convolutional Neural Network on FPGA[J]. Journal of Systems Architecture, 2019, 97:278-286. DOI:10.1016/j.sysarc.2018.12.008http://doi.org/10.1016/j.sysarc.2018.12.008https://linkinghub.elsevier.com/retrieve/pii/S1383762118304612https://linkinghub.elsevier.com/retrieve/pii/S1383762118304612
KNAPHEIDE J, STABERNACK B, KUHNKE M. A High Throughput MobileNetV2 FPGA Implementation Based on a Flexible Architecture for Depthwise Separable Convolution[C]// 2020 30th International Conference on Field-Programmable Logic and Applications(FPL).Piscataway:IEEE, 2020:277-283.
YAN J, YIN S, TU F, et al. GNA:Reconfigurable and Efficient Architecture for Generative Network Acceleration[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018, 37(11):2519-2529. DOI:10.1109/TCAD.2018.2857258http://doi.org/10.1109/TCAD.2018.2857258https://ieeexplore.ieee.org/document/8412607/https://ieeexplore.ieee.org/document/8412607/
ZHANG X, DAS S, NEOPANE O, et al. A Design Methodology for Efficient Implementation of Deconvolutional Neural Networks on an FPGA(2017)[J/OL].[2020-01-01]. https://arxiv.org/abs/1705.02583v1https://arxiv.org/abs/1705.02583v1https://arxiv.org/abs/1705.02583v1.
LIU S, FAN H, NIU X, et al. Optimizing CNN-Based Segmentation with Deeply Customized Convolutional and Deconvolutional Architectures on FPGA[J]. ACM Transactions on Reconfigurable Technology and Systems, 2018, 11(3):1-22.
XIA L, DIAO L, JIANG Z, et al. PAI-FCNN:FPGA Based Inference System for Complex CNN Models[C]// 2019 IEEE 30th International Conference on Application-Specific Systems,Architectures and Processors(ASAP).Piscataway:IEEE, 2019:107-114.
BAI L, LYU Y, HUANG X. A Unified Hardware Architecture for Convolutions and Deconvolutions in CNN[C]// 2020 IEEE International Symposium on Circuits and Systems(ISCAS).Piscataway:IEEE, 2020:1-5.
DI X K, YANG H G, HUANG Z H, et al. Exploring Resource-Efficient Acceleration Algorithm for Transposed Convolution of GANs on FPGA[C]// 2019 International Conference on Field-Programmable Technology(ICFPT).Piscataway:IEEE, 2019:19-27.
DI X K, YANG H G, JIA Y P, et al. Exploring Efficient Acceleration Architecture for Winograd-Transformed Transposed Convolution of GANs on FPGAs[J]. Electronics, 2020, 9(2):1-21. DOI:10.3390/electronics9010001http://doi.org/10.3390/electronics9010001https://www.mdpi.com/2079-9292/9/1/1https://www.mdpi.com/2079-9292/9/1/1
CHANG J, AHN S, KANG K, et al. Towards Design Methodology of Efficient Fast Algorithms for Accelerating Generative Adversarial Networks on FPGAs[C]// 2020 25th Asia and South Pacific Design Automation Conference(ASP-DAC).Piscataway:IEEE, 2020:283-288.
须颖, 刘帅, 邵萌, 等. 一种多尺度GAN的低剂量CT超分辨率重建方法[J]. 西安电子科技大学学报, 2022, 49(2):228-236.
XU Yin, LIU Shuai, SHAO Meng, et al. Multi-Scale Generation Antagonistic Network for the Low-Dose CT Images Super-Resolution Reconstruction Algorithm[J]. Journal of Xidian University, 2022, 49(2):228-236.
高杰, 霍智勇. 一种门控卷积生成对抗网络的图像修复算法[J]. 西安电子科技大学学报, 2022, 49(1):216-224.
GAO Jie, HUO Zhiyong. Algorithm for Image Inpainting in Generative Adversarial Networks Based on Gated Convolution[J]. Journal of Xidian University, 2022, 49(1):216-224.
李斌, 齐延荣, 周清雷. 基于Winograd算法的目标检测加速器设计与优化[J]. 电子学报, 2022, 50(10):2387-2397. DOI:10.12263/DZXB.20201371http://doi.org/10.12263/DZXB.20201371
LI Bin, QI Yanrong, ZHOU Qinglei. Design and Optimization of Target Detection Accelerator Based on Winograd Algorithm[J]. Acta ElectronicaSinica, 2022, 50(10):2387-2397.
HUANG C C, DONG X X, LI Z, et al. Efficient Stride 2 Winograd Convolution Method Using Unified Transformation Matrices on FPGA[C]// 2021 International Conference on Field-Programmable Technology(ICFPT).Piscataway:IEEE, 2021:1-9.
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